1. Field of the Invention
The present invention relates to the field of data storage and in particular to controlling the latency and power consumption of a memory.
2. Description of the Prior Art
As memories such as DRAM increase in size and as they are mounted within systems in ever closer relation to each other and are on occasion stacked on top of each other, the power consumption of these memories may need to be controlled to avoid them overheating.
With DRAM memories for example, there is significant power consumed when a line or row in the DRAM is activated. FIG. 1 shows an example of a conventional DRAM memory bank 5 consisting of 8 banks of memory 10. These memory banks are formed of arrays of data storage locations and an activation of a row in response to a row address in a data access will result in sense amplifiers 12 being fired and either the data that is stored in capacitors within the row being discharged onto the sense amplifiers, or data being written to the sense amplifiers and in the following precharge phase being stored in the capacitors in the row.
For a read for example, once the data from a row is stored in the sense amplifiers it may be accessed in dependence upon a column address input to multiplexer 14 and if several columns in the same row are accessed only one raw will need to be activated for the access of these several items. However, the transferring of the data will take some time and will limit the activation rate for the memory. This is illustrated by the graph in FIG. 1 that shows how activation time changes with the length of the packet size, that is the number of bits of data output for the row. If only one or a very few data items from a row are accessed, then this does not take long and a subsequent access to a different memory bank can occur quite quickly. As these accesses all require row activation and subsequent precharge this can result in relatively large power consumption of the memory and this can lead to overheating. Thus, memories are generally designed with a minimum access time between subsequent accesses or row activations and a further constraint of a minimum time for four row accesses tFAW.
Thus, for example the time between accesses may be limited by the design to be greater than 7.5 ns, while the time for four accesses may be limited to be above 35 ns. These limits are set by the designer of the memory but may not be sufficient to protect the memory from overheating where the memory is mounted in a stack for example. It may also not be sufficient to protect other components within a processing apparatus, and thus, further constraints may need to be applied to limit the speed of access of the memory and thus, its power consumption.
However, limiting the access speed to a memory increases its latency and decreases the performance of devices using the memory. It would be desirable to reduce power consumption without unduly affecting performance.